The present invention relates to a memory unit address transform definition system and a method of defining transforms. The present invention may be used, for example, for identification of address transformation from a logical address space into a topological address space in solid state memory devices, including semiconductor, ferro-electric, optical, holographic, molecular and crystalline atomic memories.
The present invention is applicable in particular, though not exclusively, in test systems for engineering test analysis, for example, for processing and representation of defect data, or in memory redundancy allocation systems for establishing a relationship between memory unit addresses in different memory device topologies for the purposes of distribution of spare resources.
In the memory industry, large electronic systems are produced having hundreds of integrated circuits designed to implement a large number of logical functions. These functions are implemented by the logical design of the system. However, the actual physical structure of the system which specifies the actual physical locations of the electronic components necessary to implement the logical, i.e. electrical, functions, differs from the logical design.
At present, the size and density of memory products is increasing exponentially over time: from 210 bits in 1971 to more than 228 bits being sampled by manufacturers today. As the density of memory devices increases, the number of defects in them increases as well. To properly test a memory device, a detailed description of the internal topology and address mapping of the device is required in order to run complex redundancy schemes and optimize testing procedures.
To test memory products after fabrication, different test methods are used, some of them being independent of the physical location of the memory cell, but most requiring knowledge of the placement of every cell. The address presented to the memory device is called the logical address; this may not be the same as the address used to access the physical memory cell or cells, which is called the topological address. (See A. J. van de Goor xe2x80x9cTesting Semiconductor Memories: Theory and Practicexe2x80x9d, publ. by John Wiley and Sons, 1996, pp. 429-436).
The translation of logical addresses into topological addresses is called address transformation, mapping, or scrambling. When addresses are transformed, successive logical addresses may transform into non-successive topological addresses. One reason for this difference is that decoders are restricted in size in order to fit the topology of rows and columns of memory cells. A second reason is that, to maintain acceptable production yields, redundant cells are added during manufacture that can be used to replace faulty cells. Spare rows and columns cause a difference in the logical and topological address sequence. Lastly, different device designs result in device layouts in which on-device address pads do not correspond to the standard pin numbers.
There are several transformation procedures described in An Interactive Descrambler Program for RAMs with Redundancy, Kirschner, N. In Proc. IEEE Int. Test Conference, pp. 252-257, 1982. The known transformation means can scramble the address lines of a 64 Kbit memory device using an 8-bit row address and an 8-bit column address. The equations describing the transformation operation for the row-select lines r0 through r7 are given below. To identify the mapping, each address must be calculated in accordance with the equations; there is no simple scheme provided for identifying the transformation.
r0=a0 XOR a2 XOR A7
r1=a1 XOR a2 XOR A7
r2=a2 XOR A7
r6=a6 XOR a7
r7=a7
Using formulas for describing address transformation requires a tremendous amount of calculation and, taking into account the trend of continuously increasing numbers of units to be addressed in a memory, known procedures are becoming too bulky to enable fast and intelligent mapping from logical into topological space and reverse mapping. Moreover, these procedures cannot provide identification of mapping schemes in cases where formulas are unknown or the memory architecture is too complex to make possible fast and effective calculations.
There are numerous mapping schemes described in the literature where transformation tables are used. For example, U.S. Pat. No. 4,774,652 describes a memory mapping scheme designed to simplify the access of pages in a cache memory system. However, these systems often make mapping definition very difficult, for example requiring a lot of routine machine work to create a large table with 2n entries. Storing the address transformation table requires too much space. Besides, reverse transformation requires the same memory space as direct transformation and is not possible where the available memory is restricted.
A computer design system for mapping a logical hierarchy into a physical hierarchy has been proposed in U.S. Pat. No. 5,455,775. The logical hierarchy contains several levels of logical entities connected by signals. The mapping is accomplished by physically allocating each of the logical entities to a specific physical component and storing lists of these logical entities and signal classifications. The known system simplifies mapping in that it permits the automatic generation of physical designs for an electronic layout and does not require the creation of large transformation tables. However, this technique cannot be used for reverse mapping, nor for defining the mapping where the transformation formulas are unknown.
Moreover, in some applications it is desirable to display an enlarged view of the die containing the semiconductor device and the locations that produced error data (see U.S. Pat. No. 5,720,031). Typically, complex algorithms are required to perform logical-to-physical and then physical-to-spatial mapping in order to display error data properly.
A simple mapping means and procedure has been proposed in PCT/RU98/00403, filed Nov. 30, 1998 (priority UK 9725066.6), published Jul. 22, 1999, WO 99/37083. The known means are capable of a configurable mapping represented as an affine transformation in Pn space, where n is the total number of bits in an address, and P is the modulo 2 field. The transformation map is stored as an nxc3x97n matrix of bits and an nxc3x971 translation vector. The known means permits direct and reverse mapping and provides a fast and cost-effective mapping procedure. To perform address transformation, the known means also uses transformation formulas.
However, in some applications transformation formulas are unknown, for example, when they are not given explicitly by the memory manufacturer. Such instances produce represents serious problems during testing or incoming inspection by the end user or buyer.
Thus, the problem of defining transformation remains when the transformation formulas are unknown.
It is an object of the present invention to overcome at least one of the above drawbacks of the prior art and provide a user-friendly means capable of fast and easy identification of address transformation of memory unit addresses between different memory device topologies when transformation formulas are unknown and a method for defining transforms memory device addresses, with the advantages of reducing the required memory space and the time required for transformation.
According to one aspect of the invention, a transform definition system is provided for the identification of transformations of memory device addresses between different memory device topologies, each topology having a corresponding address space, the system comprising:
a receiving means for receiving a representative plurality of pairs of addresses, each pair consisting of one memory cell address in the first address space and one address in the second address space;
an address pairs storage means for storing said pairs of addresses; and
a computing means for computing the transformation formulas.
Preferably, the system according to the present invention further comprises a means for collecting and storing information about transformation, i.e. the transformation map, as an nxc3x97n matrix of bits and an nxc3x971 translation vector, where n is the total number of bits in an address.
The transformation formulas obtained according to the present invention may be used in any affine transformation means for address transformation, preferably, in an affine transformation means capable of representing mapping as an affine transformation in Pn space, where n denotes the total number of bits in an address, and P is the modulo 2 field, which is described in PCT/RU98/00403.
Still another aspect of the present invention is a method of defining transforms of memory device addresses between different memory device topologies, each topology having a corresponding address space, including;
receiving a representative plurality of pairs of addresses, each pair consisting of one memory cell address in the first address space and one address in the second address space,
storing said pairs, and
computing the transformation formulas.
Preferably, the method further comprises initializing affine transformation means using the obtained transformation formulas.
The proposed method of defining transforms may also be computer-implemented permitting fast and extremely easy address identification without the necessity of performing complex intellectual work and routine machine calculations.
According to the invention, a computer program product comprises:
a computer usable medium having computer readable program code means embodied in said medium for defining transforms of memory device addresses between different memory device topologies, each topology having a corresponding address space, said computer readable program code means comprising:
a computer readable program code means for causing a computer to receive a representative plurality of pairs of addresses, each pair consisting of one memory cell address in the first address space and one address in the second address space;
a computer readable program code means for causing a computer to store said pairs; and
a computer readable program code means for causing a computer to generate transformation formulas.
Preferably, the proposed computer program product further comprises a computer readable program code means for causing a computer to transfer the transformation formulas to initialise an affine transformation means.
Still another aspect of the present invention is a computer readable memory operable in a computer, comprising a computer program for performing the above mentioned computer implemented method.
According to the invention, a system and a method for defining transforms may be used for different address transformations, for example, from logical into topological address space for engineering purposes, from logical into an address space appropriate for the purposes of allocating spare resources and laser repair procedures, or into an address space suitable for displaying errors stored in the form of a fault bit map, the transformation being a configurable mapping represented as an affine transformation.
It shall also be mentioned that an important feature of the present invention is that it is applicable for the identification of transformations independently of its direction, thereby providing identification of both direct and reverse transforms within the same procedure.
The term xe2x80x9ca memory cellxe2x80x9d as used herein is an example of a memory addressable unit and shall not be interpreted as a limiting feature. In general, any addressable memory device falls within the scope of the present invention and may be treated in accordance with the proposed procedures, including a memory tile, memory cell, or any other addressable unit within the memory device.
The terms xe2x80x9ca transform definition systemxe2x80x9d, or xe2x80x9ca system for defining transformsxe2x80x9d are used herein to denote a system capable of defining, or identifying, transforms, i.e. transformations, of memory device addresses between different memory device topologies.
The proposed system may also comprise a means for collecting and storing information about transformations in the form of a transformation map. The transformation map may be stored as an nxc3x97n matrix of elements (e.g., bits) and an nxc3x971 translation vector, where n is the total number of bits in an address.
For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made, by way of example, without loss of generality, to the accompanying drawings in which: